Users of modern electronic devices, such as, for example, portable computers, mobile phones, accessories therefore, etc. appreciate robustness and high reliability, long battery lifetimes, compatibility between the devices and other features. Advances in very large scale integration (VLSI) fabrication techniques for integrated circuits (IC) are often based on reduced transistor dimensions (e.g., channel length) without a proportional scaling of the supply voltages. The reduction of critical transistor dimensions results in a significant increase of the electrical fields in the transistors. Also, circuits with different supply voltages might be connected to each other. For example, a first circuit (hereinafter conveniently called "interface") operates at a low supply voltage VCCL (e.g., 3.3 volts, "L" for "low") and controls a second circuit (e.g., a computer) operating at a higher supply voltage VCCH (e.g., 5 volts, "H" for "high"). The computer might from time to time pull outputs nodes of the interface to the high voltage VCCH. Thereby, the voltage VCCH from the computer goes partly into the interface and becomes an "overvoltage" for the interface. To avoid damages at, for example, output transistors at the interface, a further propagation of the high voltage VCCH should be avoided. The output transistors themselves should also accommodate VCCH. Leakage currents flow from the computer (at VCCH) back to the interface (at VCCL) and contribute to parasitic power consumption. The interface should be protected from overvoltages even if its supply voltage is grounded (at e.g., zero volts) or floating.
CMOS-circuits have inherently parasitic bipolar transistors and thyristors which form silicon controlled rectifiers (SCR). Under overvoltage conditions, these SCR can cause unwanted effect known as "latch-up". The following references give more details: [1] Whitaker, J. C. (editor): "The Electronics Handbook", Technical Press, Beaverton, Oreg., 1996, ISBN 0-8493-8345-5, chapter 47.3 "CMOS Logic" on pages 679-683; and [2] Horowitz, P., Hill, W.: "The Art of Electronics", Second Edition, Cambridge University Press, 1989, ISBN 0-521-37095-7, chapter 14.16 "Keeping CMOS Low Power" on pages 970-974. Circuits are, for example, described in European Patent 414 353 B 1 to Lundberg [3]; and in U.S. Pat. No. 4,521,698 to Taylor [4]. Some circuits employ enhancement and depletion transistors. Such solutions require cost intensive manufacturing steps to implement the depletion transistors.
Hence, the present invention seeks to provide an improved circuit and a method which mitigate or avoid these and other disadvantages and limitations of the prior art.